Shanghai, China

Jiajun Fan


Average Co-Inventor Count = 6.0

ph-index = 1


Company Filing History:


Years Active: 2024

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2 patents (USPTO):Explore Patents

Title: Innovations of Jiajun Fan in Machine Learning and Delay Estimation

Introduction

Jiajun Fan is a prominent inventor based in Shanghai, China. He has made significant contributions to the field of electronic design automation, particularly in the area of delay estimation using machine learning techniques. With a total of 2 patents, his work is paving the way for more efficient and accurate electronic designs.

Latest Patents

Jiajun Fan's latest patents include innovative methods for integrating machine learning into delay estimation for FPGA-based emulation systems. One of his notable patents focuses on a method or system for estimating delays in design under tests (DUTs) using machine learning. This system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Another patent by Jiajun Fan involves a delay estimation system that estimates the delay of a DUT for an emulation system. This system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. It applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Career Highlights

Jiajun Fan is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to focus on innovative solutions that enhance the design and emulation processes in the electronics industry.

Collaborations

Throughout his career, Jiajun Fan has collaborated with notable colleagues, including Yanhua Yi and Yu Yang. These collaborations have contributed to the advancement of technologies

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