Synopsys, Inc.

Yu Yang

Jianfeng Huang

Yanhua Yi

Vinod Kumar Nakkala

Vijay Sundaresan

Jiajun Fan

Shih-Ying Liu

A method or system for estimating delays in design under tests (DUTs) using machine learning. The system accesses multiple DUTs, each comprising various logic blocks. For each DUT, a combinatorial path is identified, connecting one or more logic blocks. A feature vector is generated, including values of orthogonal features representing the combinatorial path's characteristics. Each DUT is compiled for emulation, and the delay of its combinatorial path is measured. These measured delays, along with the corresponding feature vectors, are used to train a machine learning delay model. The trained model is designed to receive a combinatorial path of a DUT as input and generate an estimated wire delay as output. This approach leverages machine learning to predict delays in electronic designs, improving the efficiency and accuracy of delay estimations in complex circuits.

Integrating machine learning delay estimation in FPGA-based emulation systems

A delay estimation system estimates a delay of a DUT for an emulation system. The delay estimation system receives logic blocks of the DUT and a combinatorial path connecting one or more of the logic blocks. The system applies a delay model to a feature vector representing the combinatorial path, where the delay model can determine a delay of the combinatorial path. The delay model may be a machine learning model. The system generates a timing graph using the determined delay and provides the timing graph to a compiler to perform placement and routing of the DUT.

Machine learning delay estimation for emulation systems

A method includes generating a channel configuration between a first signal pin of a first integrated circuit (IC) die and a second signal pin of a second IC die based on a multiplex data rate (XDR) of the first signal pin and the second signal pin. The channel configuration includes an association of the XDR to a channel. The method also includes determining a signal pin channel assignment based on the channel configuration, updating the channel configuration based on the signal pin channel assignment and a wirelength representative of a total distance between the first signal pin, the second signal pin, and physical ports of the channel, and performing socket instantiation based on the updated channel configuration and the signal pin channel assignment.

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Shanghai, China

Yu Yang