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For the Inventor, By the Inventor

Taoyuan, Taiwan

Yu-Te Hsieh

This inventor holds 23 USPTO granted patents and 21 published patent applications and 1 EPO patent, primarily in Semiconductor Packaging. Top assignees: Semiconductor Components Industries, LLC, Industrial Technology Research Institute. Active years: 2003-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yu-Te Hsieh. Retrieved from https://idiyas.com/inventor/yu-te-hsieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 23 

% Patents Active = 87.0

 

Average Co-Inventor Count = 1.4

ph-index = 4

Forward Citations = 162(Granted Patents)


Company Filing History:

goldMedal19 out of 3,735 
 
Semiconductor Components Industries, LLC
 patents
silverMedal4 out of 9,312 
 
Industrial Technology Research Institute
 patents

Years Active: 2003-2026

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Areas of Expertise:
Image Sensor Packaging
Multi-Chip Packaging
Wafer Level Packaging
Contamination Barrier
Light Blocking Member
Gap Height Definition
High Reliability Housing
IC Chip Bonding
Dummy Bumps
Electrically Conductive Bumps
Semiconductor Die
Package Structures
23 patents (USPTO):Explore Patents
1. 12532559 - Image sensor packaging structures and related methods (2026-01-20),
2. 12317628 - Image sensor package (2025-05-27),
3. 12237351 - Semiconductor package structure and related methods (2025-02-25),
4. 12107105 - Method for defining a gap height within an image sensor package (2024-10-01),
5. 12068345 - Image sensor package having a light blocking member (2024-08-20),
6. 11869912 - Method for defining a gap height within an image sensor package (2024-01-09),
7. 11508776 - Image sensor semiconductor packages and related methods (2022-11-22),
8. 11476292 - Multi-chip packaging structure for an image sensor (2022-10-18),
9. 11444111 - Image sensor package having a light blocking member (2022-09-13),
10. 11037970 - Semiconductor package structure and related methods (2021-06-15),
11. 10790208 - High reliability wafer level semiconductor packaging (2020-09-29),
12. 10714454 - Stack packaging structure for an image sensor (2020-07-14),
13. 10707257 - Multi-chip packaging structure for an image sensor (2020-07-07),
14. 10290672 - Image sensor semiconductor packages and related methods (2019-05-14),
15. 10290556 - High reliability wafer level semiconductor packaging (2019-05-14),

Title: Inventor Yu-Te Hsieh: Revolutionizing Technology in Taoyuan

Introduction: Yu-Te Hsieh is a pioneering inventor based in Taoyuan, Taiwan, known for her groundbreaking contributions to the field of technology and innovation.

Latest Patents: Yu-Te Hsieh holds several patents in the areas of artificial intelligence, renewable energy, and sustainable technologies, showcasing her commitment to creating a more sustainable future.

Career Highlights: With a career spanning over two decades, Yu-Te Hsieh has worked with leading tech companies and research institutions to develop cutting-edge solutions that have had a significant impact on various industries.

Collaborations: Throughout her career, Yu-Te Hsieh has collaborated with top researchers, engineers, and scientists from around the world, fostering a culture of innovation and knowledge-sharing.

Conclusion: Yu-Te Hsieh's relentless pursuit of innovation and her passion for creating a better world through technology make her a true visionary in the field of inventions.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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