Tokyo, Japan

Yoko Hayashida

This inventor holds 3 USPTO granted patents and 1 published patent application. Top assignees: Elpida Memory, Inc., Other. Active years: 2004-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yoko Hayashida. Retrieved from https://idiyas.com/inventor/yoko-hayashida

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 3 

% Patents Active = 100.0

Average Co-Inventor Count = 1.3

ph-index = 2

Forward Citations = 11(Granted Patents)


Company Filing History:


Years Active: 2004-2008

Loading Chart...
3 patents (USPTO):Explore Patents

Title: Yoko Hayashida: Innovator in Semiconductor Technology

Introduction

Yoko Hayashida is a prominent inventor based in Tokyo, Japan. She has made significant contributions to the field of semiconductor technology, particularly in the development of integrated circuit devices. With a total of 3 patents to her name, her work has had a substantial impact on the industry.

Latest Patents

One of her latest patents is focused on a semiconductor integrated circuit device with protection capability for protection circuits from static electrical charge. This innovation involves the formation of semiconductor integrated circuit (IC) devices, such as diodes and MOSFETs, that protect circuits from Electrostatic Discharge (ESD). The design includes an N+ (or P+) and P+ (or N+) diffusion layers within an N (or P) well on a P (or N) type semiconductor substrate. The N+ (or P+) diffusion layer of the diode is connected to the power supply. Additionally, an NMOSFET (or PMOSFET) is formed with N+ (or P+) source/drain regions and a gate on the same P (or N) type substrate. The P+ (or N+) diffusion layer of the diode and the N+ (or P+) source/drain regions of the NMOSFET (or PMOSFET) are connected to a fuse through second and first levels of metal wirings.

Another significant patent is for a semiconductor integrated circuit device and method for designing the same. This invention provides greater flexibility of layout while ensuring circuit characteristics. It also offers a minimum electrostatic discharge breakdown withstand value according to the Charged Device Model (CDM) at all input/output (I/O) terminals. The size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, MOSFETs that can constitute an internal circuit, and an input resistance.

Career Highlights

Yoko has worked with notable companies in the semiconductor industry, including Elpida Memory, Inc. Her experience in these organizations has allowed her to refine her skills and contribute to groundbreaking innovations in semiconductor technology.

Collaborations

Throughout her career, Yoko has collaborated with talented individuals such as Hiroshi Furuta and Kiminori Hayano. These partnerships have fostered a creative environment that has led to the development

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…