This inventor holds 3 USPTO granted patents. Top assignee: Synopsys, Inc.. Active years: 2011-2020.
Location History:
- Karnataka, IN (2011)
- Bengaluru, IN (2017 - 2020)
Company Filing History:
Years Active: 2011-2020
Title: Innovations by Yogesh Pandey
Introduction
Yogesh Pandey is a notable inventor based in Bengaluru, India. He has made significant contributions to the field of electronic design verification. With a total of 3 patents to his name, his work focuses on enhancing the efficiency and accuracy of circuit design verification processes.
Latest Patents
Yogesh's latest patents include innovative methods for verifying circuit designs. One of his patents, titled "Automatic definition and extraction of functional coverage metric for emulation-based verification," outlines a method that involves identifying groups of signals associated with a circuit. This method includes selecting a signal sampling window depth and performing verifications using test benches to generate functional coverage metrics. The process also involves comparing these metrics and automatically generating cover property statements to ensure that the second functional coverage meets or exceeds the first.
Another significant patent is "Assertion extraction from design and its signal traces." This invention identifies groups of signals in electronic designs for which assertions can be generated. It utilizes a sliding temporal window to sample unique value combinations of signals and organizes these values into truth tables. The patent details the extraction of minimal functional relations and the generation of syntactically correct assertion statements for further verification processes.
Career Highlights
Yogesh Pandey is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys focuses on developing advanced verification methodologies that enhance the reliability of electronic designs. His contributions have been instrumental in pushing the boundaries of what is possible in circuit design verification.
Collaborations
Yogesh has collaborated with several talented individuals in his field, including Saptarshi Ghosh and Eduard Rudolf Cerny. These collaborations have fostered an environment of innovation and have led to the development of cutting-edge verification techniques.
Conclusion
Yogesh Pandey's contributions to electronic design verification through his patents and work at Synopsys, Inc. highlight his role as a key innovator in the field. His inventions not only improve the verification process but also set new standards for future developments in electronic design.