The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 24, 2020

Filed:

Mar. 08, 2019
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Saptarshi Ghosh, Bangalore, IN;

Yogesh Pandey, Bangalore, IN;

Sivaprasad Acharya, Singapore, SG;

Eduard Cerny, Marlborough, MA (US);

Assignee:

SYNOPSYS, INC., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/20 (2020.01); G06F 30/398 (2020.01);
U.S. Cl.
CPC ...
G06F 30/398 (2020.01); G06F 30/20 (2020.01);
Abstract

A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.


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