Yiding Han

Title: Yiding Han and Chip Interconnect Planning

Introduction

Yiding Han is an inventor based in Mountain View, California, and works at Synopsys, Inc. His patent work addresses chip design and interconnect planning. The available information credits him with 1 patent.

Latest Patents

Han’s listed patent is “Fast Topology Bus Router for Interconnect Planning.” It describes a method that receives a chip netlist containing a bus and determines a routing topology through a chip’s routing region. The method compares the bus’s routing demand with the capacity of cells in that region, then generates a chip layout based on the selected topology.

Career Highlights

Han’s listed invention focuses on automating a key aspect of chip layout planning: choosing a bus-routing topology in view of available routing capacity. This approach connects netlist analysis with the generation of a physical chip layout.

Collaborations

The provided information lists David L. Peart and Douglas Chang as Han’s coworkers. Their names are associated here as workplace colleagues; no specific role in the patent is stated.

Conclusion

Yiding Han’s listed patent reflects work on efficient bus routing and chip interconnect planning, connecting routing-capacity analysis with chip-layout generation.