The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 04, 2023
Filed:
Jun. 11, 2021
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventors:
Zhengtao Yu, Mountain View, CA (US);
Balkrishna Rashingkar, Mountain View, CA (US);
David Peart, Mountain View, CA (US);
Douglas Chang, Mountain View, CA (US);
Yiding Han, Mountain View, CA (US);
Assignee:
Synopsys, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/392 (2020.01); G06F 119/18 (2020.01);
U.S. Cl.
CPC ...
G06F 30/394 (2020.01); G06F 30/392 (2020.01); G06F 2119/18 (2020.01);
Abstract
A method includes receiving a netlist for a chip including a bus and determining, by one or more processors and based on the netlist, a first routing topology for the bus and through a routing region of the chip by comparing a demand of the bus to a capacity of a plurality of cells of the routing region. The method also includes generating a layout for the chip based on the first routing topology.