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For the Inventor, By the Inventor

Chandler, AZ, United States of America

Yeon Ho Choi

This inventor holds 11 USPTO granted patents. Top assignees: Amkor Technology, Inc., Other. Active years: 2001-2013.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yeon Ho Choi. Retrieved from https://idiyas.com/inventor/yeon-ho-choi

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 11

% Patents Active = 100.0

Average Co-Inventor Count = 1.9

ph-index = 8

Forward Citations = 391(Granted Patents)


Location History:

  • Seoul, KR (2001 - 2002)
  • Chandler, AZ (US) (2010 - 2013)

Company Filing History:

goldMedal9 out of 1,009 
 
Amkor Technology, Inc.
 patents
silverMedal2 out of 834,570 
Other
 patents

Years Active: 2001-2013

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11 patents (USPTO):Explore Patents
1. 8441110 - Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package (2013-05-14),
2. 8432023 - Increased I/O leadframe and semiconductor device including same (2013-04-30),
3. 8299602 - Semiconductor device including leadframe with increased I/O (2012-10-30),
4. 8188579 - Semiconductor device including leadframe having power bars and increased I/O (2012-05-29),
5. 7989933 - Increased I/O leadframe and semiconductor device including same (2011-08-02),
6. 7968998 - Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package (2011-06-28),
7. 7875963 - Semiconductor device including leadframe having power bars and increased I/O (2011-01-25),
8. 7847392 - Semiconductor device including leadframe with increased I/O (2010-12-07),
9. 6437427 - Lead frame used for the fabrication of semiconductor packages and semiconductor package fabricated using the same (2002-08-20),
10. 6339252 - Electronic device package and leadframe (2002-01-15),
11. 6258629 - Electronic device package and leadframe and method for making the package (2001-07-10),

Title: Yeon Ho Choi: Innovator in Semiconductor Packaging

Introduction

Yeon Ho Choi is a prominent inventor based in Chandler, AZ (US), known for his significant contributions to the field of semiconductor packaging. With a total of 11 patents to his name, Choi has made remarkable advancements that enhance the functionality and efficiency of semiconductor devices.

Latest Patents

Choi's latest patents include innovative designs such as the "Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package." This invention features a semiconductor package with a planar die paddle that defines multiple peripheral edge segments and a plurality of leads arranged in concentric rows. The design allows for efficient electrical connections between the semiconductor die and the leads, with portions of the die paddle and leads encapsulated by a package body, ensuring durability and performance.

Another notable patent is the "Increased I/O leadframe and semiconductor device including same." This semiconductor package is designed with a uniquely configured leadframe that maximizes the number of exposed leads. The package includes a die pad and leads that are strategically arranged to enhance connectivity and performance, showcasing Choi's innovative approach to semiconductor design.

Career Highlights

Throughout his career, Yeon Ho Choi has worked with notable companies, including Amkor Technology, Inc. His experience in the semiconductor industry has allowed him to develop cutting-edge technologies that address the evolving needs of electronic devices.

Collaborations

Choi has collaborated with talented individuals such as Gi Jeong Kim and Eulogia A Niones, contributing to the advancement of semiconductor packaging technologies through teamwork and shared expertise.

Conclusion

Yeon Ho Choi's contributions to semiconductor packaging have significantly impacted the industry, with his innovative patents paving the way for enhanced electronic devices. His work exemplifies the importance of creativity and collaboration in driving technological advancements.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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