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For the Inventor, By the Inventor

Inagi, Japan

Yasushi Yasuda

This inventor holds 9 USPTO granted patents. Top assignee: Fujitsu Corporation. Active years: 1981-1989.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasushi Yasuda. Retrieved from https://idiyas.com/inventor/yasushi-yasuda

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 9

% Patents Active = 100.0

Average Co-Inventor Count = 4.1

ph-index = 5

Forward Citations = 62(Granted Patents)


Location History:

  • Machida, JP (1986 - 1988)
  • Inagi, JP (1981 - 1989)

Company Filing History:

goldMedal9 out of 39,371 
 
Fujitsu Corporation
 patents

Years Active: 1981-1989

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9 patents (USPTO):Explore Patents
1. 4888623 - Semiconductor device with PN junction isolation for TTL or ECL circuits (1989-12-19),
2. 4774620 - Logic circuit (1988-09-27),
3. 4703202 - Two-stage gate circuit providing inverted and non-inverted outputs (1987-10-27),
4. 4680600 - Semiconductor device (1987-07-14),
5. 4567380 - Schmitt trigger circuit (1986-01-28),
6. 4449063 - Logic circuit with improved switching (1984-05-15),
7. 4409495 - Schmitt trigger circuit with low input current (1983-10-11),
8. 4388755 - Structure for and method of manufacturing a semiconductor device by the (1983-06-21),
9. 4276556 - Semiconductor device (1981-06-30),

Title: Yasushi Yasuda: Innovator in Semiconductor Technology

Introduction

Yasushi Yasuda is a prominent inventor based in Inagi, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 9 patents. His work focuses on enhancing the performance and reliability of semiconductor devices.

Latest Patents

Yasuda's latest patents include innovative designs that address critical issues in semiconductor functionality. One notable patent is for a semiconductor device with PN junction isolation for TTL or ECL circuits. This invention prevents electrostatic breakage of a semiconductor device by forming an impurity region in the epitaxial layer, creating a PN junction between the buried layer and the impurity region. This region is connected to a power source or ground, enhancing device stability.

Another significant patent is for a logic circuit that reduces the occurrence of breakdown in the pull-down and pull-up transistors during high voltage applications. This logic circuit ensures high voltage resistance by controlling the transistors based on the collector and emitter voltages. A protection circuit is included to discharge the base of the pull-down transistor, turning it off when voltage differences exceed a specified value.

Career Highlights

Yasushi Yasuda has built a successful career at Fujitsu Corporation, where he has been instrumental in advancing semiconductor technologies. His expertise and innovative approach have led to numerous patents that contribute to the company's reputation as a leader in the tech industry.

Collaborations

Throughout his career, Yasuda has collaborated with talented individuals such as Hiromu Enomoto and Akinori Tahara. These collaborations have fostered a creative environment that has resulted in groundbreaking innovations in semiconductor technology.

Conclusion

Yasushi Yasuda's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the field. His work continues to influence the development of reliable and efficient semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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