The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 27, 1987

Filed:

Feb. 11, 1985
Applicant:
Inventors:

Hiromu Enomoto, Kawasaki, JP;

Yasushi Yasuda, Machida, JP;

Akinori Tahara, Zushi, JP;

Masao Kumagai, Tokyo, JP;

Assignee:

Fujitsu Limited, Kanagawa 211, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ;
U.S. Cl.
CPC ...
307443 ; 307446 ; 307456 ; 307458 ; 307480 ;
Abstract

A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.


Find Patent Forward Citations

Enomoto, Hiromu. (1987). Two-stage gate circuit providing inverted and non-inverted outputs (U.S. Patent No. 4703202). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4703202

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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