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For the Inventor, By the Inventor

Zushi, Japan

Akinori Tahara

This inventor holds 8 USPTO granted patents. Top assignee: Fujitsu Corporation. Active years: 1986-1999.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Akinori Tahara. Retrieved from https://idiyas.com/inventor/akinori-tahara

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 8

% Patents Active = 100.0

Average Co-Inventor Count = 3.7

ph-index = 5

Forward Citations = 50(Granted Patents)


Location History:

  • Zushi, JP (1986 - 1989)
  • Kawasaki, JP (1996 - 1999)

Company Filing History:

goldMedal8 out of 39,374 
 
Fujitsu Corporation
 patents

Years Active: 1986-1999

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8 patents (USPTO):Explore Patents
1. 6002155 - Semiconductor integrated circuit with protection circuit against (1999-12-14),
2. 5672895 - Semiconductor integrated circuit with protection circuit against (1997-09-30),
3. 5500542 - Semiconductor integrated circuit with protection circuit against (1996-03-19),
4. 4888623 - Semiconductor device with PN junction isolation for TTL or ECL circuits (1989-12-19),
5. 4774620 - Logic circuit (1988-09-27),
6. 4703202 - Two-stage gate circuit providing inverted and non-inverted outputs (1987-10-27),
7. 4680600 - Semiconductor device (1987-07-14),
8. 4567380 - Schmitt trigger circuit (1986-01-28),

Title: Akinori Tahara: Innovator in Semiconductor Technology

Introduction

Akinori Tahara is a prominent inventor based in Zushi, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 8 patents. His work focuses on enhancing the efficiency and reliability of integrated circuits.

Latest Patents

One of Akinori Tahara's latest patents involves a semiconductor integrated circuit with a protection circuit against electrostatic breakdown. In this innovation, diode rows are arranged at intervals in the same direction as the arrangement of cell rows. Each diode row features a series of pn junctions formed on a substrate, arranged along a track that is vertical to interconnection tracks. This design allows for automatic connections between the gates of MOS transistors and the diodes, eliminating the need to determine which gate should connect to which diode. The wiring length between the gate of the MOS transistor and the diode is kept below a specified limit to prevent electrostatic breakdown at the gate oxide during the fabrication process. Additionally, each pn junction can be strategically placed under necessary input signal lines, ground lines, the bottom of the drain of the MOS transistor, or under the power supply line outside of the macrocell.

Career Highlights

Akinori Tahara is currently employed at Fujitsu Corporation, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the capabilities of integrated circuits, making them more robust and efficient.

Collaborations

Throughout his career, Akinori has collaborated with notable colleagues, including Hiromu Enomoto and Yasushi Yasuda. These partnerships have contributed to the development of groundbreaking technologies in the semiconductor field.

Conclusion

Akinori Tahara's contributions to semiconductor technology through his patents and collaborations highlight his role as a key innovator in the industry. His work continues to influence the future of integrated circuits and their applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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