Fujitsu Corporation

Akinori Tahara

Hiromu Enomoto

Yasushi Yasuda

Isao Amano

Hiroshi Shimizu

Masao Kumagai

Yoshiki Shimauchi

Tetsuya Nakajima

Takashi Iida

Satoru Sumi

Diodes rows are arranged at interval L in the same direction as that of arrangement of cell rows. Each of the diodes rows has a row of pn junctions each formed on a substrate and arranged along a track vertical to interconnection tracks. The interconnection between cells automatically connect the gates of MOS transistors to the diodes without the need for considering which gate should be connected to the diode. The length of wiring between the gate of MOS transistor and a diode is less than an upper limit value for preventing electrostatic breakdown at a gate oxide in a process of fabricating the semiconductor integrated circuit. Each of the pn junctions may be formed under necessary input signal lines, necessary ground line, the bottom of the drain of MOS transistor or under the power supply line outside of macrocell.

Semiconductor integrated circuit with protection circuit against

Electrostatical breakage of a semiconductor device, including an epitaxial layer and a buried layer thereunder, connected to an outer signal terminal, can be prevented by forming an impurity region in the epitaxial layer so as to form a PN junction between the buried layer and the impurity region. The impurity region is connected to a power source or ground.

Semiconductor device with PN junction isolation for TTL or ECL circuits

A logic circuit which reduces occurrence of breakdown of the pull-down transistor and pull-up transistor in the output stage when a high voltage is applied to the power supply line and ensures high voltage resistance. The logic circuit controls a pull-up transistor provided between a first power supply and an output terminal which turns ON and OFF in accordance with a collector voltage of a phase splitter transistor and controls the pull-down transistor provided between the second power supply and output terminal with an emitter voltage. Breakdown of the pull-down and pull-up transistors can be reduced and a high voltage resistance ensured by providing a protection circuit which discharges the base of the pull-down transistor and turns OFF the pull-down transistor by detecting when a voltage difference between the first power supply and the second power supply exceeds a specified value.

Logic circuit

A gate circuit used for controlling an interface circuit in a microcomputer system, including a first-stage gate circuit, a second-stage gate circuit, and a control device connected between the first-stage gate circuit and the second-stage gate circuit. The first-stage gate circuit outputs an inverted strobe signal to the interface circuit, and the second-stage gate circuit outputs a non-inverted strobe signal to the interface circuit. Although there is a time lag in the changeover timing of these strobe signals, this time lag is reduced by connected the diode between the first-stage gate circuit and the second-stage gate circuit.

Two-stage gate circuit providing inverted and non-inverted outputs

A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region. The reverse withstand voltage of the PN junction type protection diode is smaller than that of the clamp diode, thereby preventing excessive reverse current flow and avoiding permanent destruction of the clamp diode.

Semiconductor device

A level shift element is connected between a transistor (Tr.sub.5) which is used to determine a threshold level when the input voltage falls and a diode (D.sub.3) is connected between an input terminal and an output control transistor (Tr.sub.2) to discharge the base of the output control transistor. The level shift element comprises a diode connected in the forward direction or a resistor.

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Zushi, Japan

Akinori Tahara