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Yasumasa Ikezaki

This inventor holds 3 USPTO granted patents. Top assignee: Texas Instruments Corporation. Active years: 2001-2005.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Yasumasa Ikezaki. Retrieved from https://idiyas.com/inventor/yasumasa-ikezaki

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 3

% Patents Active = 100.0

Average Co-Inventor Count = 3.3

ph-index = 2

Forward Citations = 13(Granted Patents)

Location History:

Matsudo, JP (2001 - 2002)
Ibaraki, JP (2005)

Company Filing History:

3 out of 29,901

Texas Instruments Corporation

Years Active: 2001-2005

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3 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 6877022 - Booth encoding circuit for a multiplier of a multiply-accumulate module (2005-04-05),

2. 6410966 - Ratio circuit (2002-06-25),

3. 6285227 - Latch ratio circuit with plural channels (2001-09-04),

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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