Yasuhisa Naruta

Title: Yasuhisa Naruta: Innovator in Semiconductor Technology

Introduction

Yasuhisa Naruta is a prominent inventor based in Kanagawa, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 3 patents. His work focuses on enhancing the performance and evaluation methods of MOS transistors.

Latest Patents

Naruta's latest patents include a simulation parameter extracting method of a MOS transistor. This method evaluates a measured value that includes a true gate-overlap capacitance by measuring capacitance between the gate and the drain across various layout patterns. The evaluation process involves subtracting a contact parasitic capacitance from the measured value to extract the true gate-overlap capacitance. Another notable patent is for a semiconductor device that includes a semiconductor evaluation element capable of analytically estimating the amount of DC variation of a MOS transistor caused by formed contacts. This evaluation element comprises a gate, diffusion layers, measurement contacts, and floating contacts, facilitating a comprehensive evaluation method.

Career Highlights

Throughout his career, Yasuhisa Naruta has worked with notable companies such as NEC Electronics Corporation and Renesas Electronics Corporation. His experience in these organizations has contributed to his expertise in semiconductor technology and innovation.

Collaborations

Naruta has collaborated with various professionals in the field, including his coworker Shigetaka Kumashiro. Their joint efforts have further advanced the research and development of semiconductor devices.

Conclusion

Yasuhisa Naruta's contributions to semiconductor technology through his innovative patents and collaborations highlight his role as a key inventor in the industry. His work continues to influence advancements in MOS transistor evaluation methods and semiconductor devices.