The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 27, 2010

Filed:

Jun. 23, 2008
Applicant:

Yasuhisa Naruta, Kanagawa, JP;

Inventor:

Yasuhisa Naruta, Kanagawa, JP;

Assignee:

NEC Electronics Corporation, Kawasaki, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a semiconductor evaluation element capable of analytically estimating the amount of DC variation of a MOS transistor which is caused by formed contacts, and an evaluation circuit and an evaluation method using the semiconductor evaluation element. The semiconductor evaluation element such as a MOS transistor includes: a gate; diffusion layers; measurement contacts; and floating contacts. The diffusion layers are formed on both sides of the gate and serve as a source and a drain. The measurement contacts are provided in positions apart from the gate on the diffusion layers. The floating contacts are provided between the gate and the measurement contacts to connect electrically isolated metal layers with the diffusion layers.


Find Patent Forward Citations

Naruta, Yasuhisa. (2010). Semiconductor device including semiconductor evaluation element, and evaluation method using semiconductor device (U.S. Patent No. 7764077). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7764077

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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