Taichung, Taiwan

Wei Hsin Lin

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Taiwan Semiconductor Manufacturing Comp. Ltd.. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wei Hsin Lin. Retrieved from https://idiyas.com/inventor/wei-hsin-lin-pc34ywum

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Wei Hsin Lin and Semiconductor Fin-Pitch Optimization

Introduction

Wei Hsin Lin is an inventor associated with Taichung, Taiwan. His patent work concerns semiconductor device design, particularly fin structures and source/drain uniformity. The supplied information lists 1 patent and identifies Taiwan Semiconductor Manufacturing Company, Ltd. as his company.

Latest Patents

Lin’s listed patent is “Fin Pitch Optimization for Uniform Source/Drain Structures.” The disclosure describes a semiconductor device with multiple fin structures formed on a substrate. The fins use alternating first and second pitches, which differ from one another. A gate structure is positioned on the fins, while a source/drain structure sits adjacent to the gate and contacts the fin structures. The design focuses on optimizing fin pitch to support substantially uniform source/drain structures.

Career Highlights

The available information connects Lin’s invention to semiconductor fabrication and device architecture. His patent addresses the arrangement of fin structures and their relationship to gate and source/drain components.

Collaborations

Hui-Hsuan Kung is identified as Lin’s coworker. The supplied information does not specify whether Kung collaborated on the patent.

Conclusion

Wei Hsin Lin’s listed patent explores how alternating fin pitches can contribute to substantially uniform source/drain structures in semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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