Hsinchu, Taiwan

Wei-Chih Shen

This inventor holds 1 USPTO granted patent. Top assignee: Realtek Semiconductor Inc.. Active years: 2021.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Wei-Chih Shen. Retrieved from https://idiyas.com/inventor/wei-chih-shen-ufw4rle7

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 1


Company Filing History:


Years Active: 2021

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Wei-Chih Shen and Clock-Gating Innovation.

Introduction

Wei-Chih Shen is an inventor based in Hsinchu, Taiwan, and is associated with Realtek Semiconductor Inc. His patent work includes a clock-gating cell designed to support clock control and scan testing.

Latest Patents

The provided patent information identifies one patent for Shen: Clock gating cell. The invention describes a cell with two latches that can be configured as a flip-flop, using positive or negative edges of a first clock signal to store an input value. A selector allows the flip-flop to choose among values from different input terminals.

The design also supports testing functions. In non-scan testing mode, an independent signal can force an unused latch closed. During scan shifting and scan capture, two independent signals can cause the cell to output the first clock signal as the gating clock signal. Shen’s listed portfolio includes 1 patent.

Career Highlights

Shen’s listed work connects him with Realtek Semiconductor Inc. and focuses on clock-gating circuitry, including features intended to support scan testing.

Collaborations

The provided information lists Yu-Cheng Lo and Jiunn-Way Miaw as Shen’s coworkers. It does not specify their roles in the patent or describe particular collaborations.

Conclusion

Wei-Chih Shen’s listed patent presents a clock-gating cell that combines selectable latch operation with controls for scan testing, reflecting his contribution to semiconductor circuit design.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…