Realtek Semiconductor Inc.

Wei-Chih Shen

Yu-Cheng Lo

Jiunn-Way Miaw

Yu-Jen Pan

Chien-Wei Shih

A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.

Growing community of inventors

Hsinchu, Taiwan

Wei-Chih Shen