The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2021
Filed:
Mar. 18, 2021
Realtek Semiconductor Corp., Hsinchu, TW;
Yu-Cheng Lo, Taichung, TW;
Yu-Jen Pan, Kaohsiung, TW;
Wei-Chih Shen, Hsinchu, TW;
Chien-Wei Shih, Hsinchu County, TW;
Jiunn-Way Miaw, Hsinchu, TW;
REALTEK SEMICONDUCTOR CORP., Hsinchu, TW;
Abstract
A clock gating cell (CGC) is provided. The clock gating cell includes two latches that can be configured as a flip-flop to use positive/negative edges of a first clock signal to store a value of an input terminal, and the clock gating cell also includes a selector used for the flip-flop to select from values of different input terminals for storing. In addition, in a non-scan testing mode, the clock gating cell can forcefully close an unused latch through an independent signal, and in a scan shift duration and a scan capture duration of a scan testing mode, the clock gating cell can further forcefully output the first clock signal as the gating clock signal according to two independent signals.