Oregon City, OR, United States of America

Warren Gray

This inventor holds 1 USPTO granted patent and 2 published patent applications. Top assignee: Intel Corporation. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Warren Gray. Retrieved from https://idiyas.com/inventor/warren-gray-kip7pfte

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0


Company Filing History:


Years Active: 2026

Loading Chart...
1 patent (USPTO):Explore Patents

Title: Warren Gray and Semiconductor Subfin Replacement

Introduction

Warren Gray is an inventor based in Oregon City, Oregon, whose patent work addresses semiconductor device design. He is associated with Intel Corporation and is named on 1 patent.

Latest Patents

Gray’s patent, “Subfins replaced using backside dielectric formation,” describes techniques for removing semiconductor subfins and replacing them with dielectric materials. The process involves removing bulk substrate material from the backside to expose the subfin, removing the subfin to create recesses, and filling those recesses with a dielectric liner and dielectric material.

The invention aims to reduce parasitic capacitance between subfins and gate electrodes, as well as parasitic current between neighboring source or drain regions. These improvements can support more effective isolation within semiconductor devices.

Career Highlights

Gray’s listed patent reflects work on semiconductor fabrication and device isolation. His association with Intel Corporation places this invention within the company’s broader semiconductor technology efforts.

Collaborations

Gray’s listed coworkers include Giorgio Mariottini and Jamie Wilt. Their names provide context for his professional connections, though the supplied information does not specify their roles in the patent.

Conclusion

Warren Gray’s patent presents a backside fabrication approach that replaces semiconductor subfins with dielectric materials to improve electrical isolation and reduce parasitic effects.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…