The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 02, 2026

Filed:

Jun. 30, 2023
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Giorgio Mariottini, Hillsboro, OR (US);

Jamie Wilt, Tualatin, OR (US);

Anbusathaiah Varatharajan, Portland, OR (US);

Jaladhi Mehta, Beaverton, OR (US);

Alexander Kane, Forest Grove, OR (US);

Amish B. Shah, Portland, OR (US);

Weihong Gao, Portland, OR (US);

Aurelia Chi Wang, Hillsboro, OR (US);

Conor P. Puls, Portland, OR (US);

Claire Mcghee, Hillsboro, OR (US);

Sayan Sarkar, Cornelius, OR (US);

Eric Young, Hillsboro, OR (US);

Timothy Lyon, Aloha, OR (US);

Chun-Kuo Huang, Portland, OR (US);

Warren Gray, Oregon City, OR (US);

Angel R. Aquino Gonzalez, Beaverton, OR (US);

Daniel J. Harris, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 62/10 (2025.01); H10D 30/67 (2025.01);
U.S. Cl.
CPC ...
H10D 62/121 (2025.01); H10D 30/6735 (2025.01);
Abstract

Techniques are provided herein to form semiconductor devices that have their semiconductor subfins removed and replaced with one or more dielectric materials. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. A lower end of the semiconductor material includes a subfin adjacent to a dielectric layer that acts as shallow trench isolation (STI) between semiconductor devices. A backside process may be performed to remove the bulk substrate and expose a bottom surface of the subfin. The subfin may then be removed from the backside to form backside recesses. A dielectric liner may be formed within the backside recesses and a dielectric fill may be formed within a remaining volume of the backside recesses. Replacing the subfins with dielectric materials may lower parasitic capacitance between the subfins and the gate electrodes as well as reduce parasitic current between adjacent source or drain regions.


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