Vvss Satyasuresh Choppalli

This inventor holds 4 USPTO granted patents. Top assignee: Globalfoundries Singapore Pte. Ltd.. Active years: 2018-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Vvss Satyasuresh Choppalli. Retrieved from https://idiyas.com/inventor/vvss-satyasuresh-choppalli

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 4

% Patents Active = 100.0

Average Co-Inventor Count = 3.3

ph-index = 2

Forward Citations = 7(Granted Patents)

Company Filing History:

4 out of 1,062

Globalfoundries Singapore Pte. Ltd.

patents

Years Active: 2018-2022

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4 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 11257808 - High holding high voltage (HHHV) FET for ESD protection with modified source and method for producing the same (2022-02-22),

2. 10453836 - High holding high voltage (HHHV) FET for ESD protection with modified source and method for producing the same (2019-10-22),

3. 10032765 - Integrated circuits with electrostatic discharge protection and methods for producing the same (2018-07-24),

4. 10032761 - Electronic devices with tunable electrostatic discharge protection and methods for producing the same (2018-07-24),

Title: Vvss Satyasuresh Choppalli: Innovator in High Voltage Technology

Introduction

Vvss Satyasuresh Choppalli is a notable inventor based in Singapore, recognized for his contributions to high voltage technology. He holds a total of 4 patents, showcasing his innovative approach in the field of electronics and semiconductor devices.

Latest Patents

His latest patents include a "High holding high voltage (HHHV) FET for ESD protection with modified source and method for producing the same." This invention involves a method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side. The process includes several steps, such as forming a DNWELL in a p-sub, creating a PWHV in the DNWELL, and establishing an NW in the DNWELL. Additionally, it involves forming STI structures through the LVPW and DNWELL, as well as creating a gate over the PWHV. The method also details the formation of multiple P+ and N+ implants, culminating in the creation of electrical contacts over these implants.

Career Highlights

Vvss Satyasuresh Choppalli is currently employed at Globalfoundries Singapore Pte. Ltd., where he continues to push the boundaries of innovation in semiconductor technology. His work has significantly impacted the development of devices that require high voltage protection.

Collaborations

He collaborates with talented coworkers, including Yohann Frederic Michel Solaro and Chai Ean Gill, contributing to a dynamic and innovative work environment.

Conclusion

Vvss Satyasuresh Choppalli exemplifies the spirit of innovation in the field of high voltage technology, with a strong portfolio of patents that reflect his expertise and dedication. His contributions continue to shape the future of semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]