Austin, TX, United States of America

Viswanath Mohan

This inventor holds 3 USPTO granted patents and 2 EPO patents. Top assignee: Via Alliance Semiconductor Co., Ltd.. Active years: 2017-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Viswanath Mohan. Retrieved from https://idiyas.com/inventor/viswanath-mohan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

 

Average Co-Inventor Count = 1.7

ph-index = 1

Forward Citations = 12(Granted Patents)


Company Filing History:


Years Active: 2017-2018

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3 patents (USPTO):Explore Patents

Title: Innovations of Viswanath Mohan

Introduction

Viswanath Mohan is a notable inventor based in Austin, TX, who has made significant contributions to the field of semiconductor technology. He holds three patents that showcase his expertise and innovative thinking in processor design and functionality.

Latest Patents

One of his latest patents is titled "System and method of distinguishing system management mode entries in a translation address cache of a processor." This invention involves a processor that includes a memory storing a system management mode (SMM) value, which indicates whether the processor is in SMM. The translation address cache (TAC) contains multiple entries for storing address translations, with each entry including an SMM identifier. The hit logic compares a lookup address with address translations stored in the TAC to determine a hit, ensuring that a hit is only recognized when the corresponding SMM identifier matches the SMM value. Additionally, the processor features flush logic that distinguishes SMM entries and processing logic that commands flushing upon entering or exiting SMM, while non-SMM entries remain intact.

Another significant patent is "Address translation cache that supports simultaneous invalidation of common context entries." This invention describes a processor that includes a mapping module for mapping architectural virtual processor identifiers to non-architectural global identifiers, as well as architectural process context identifiers to non-architectural local identifiers. The translation-lookaside buffer (TLB) contains a plurality of address translations, with each translation tagged according to whether it is a global or local address translation.

Career Highlights

Viswanath Mohan is currently employed at Via Alliance Semiconductor Co., Ltd., where he continues to innovate and contribute to advancements in semiconductor technology. His work has had a profound impact on the efficiency and functionality of processors.

Collaborations

He collaborates with talented individuals such as Colin Eddy and Terry J Parks, who share his passion for innovation and technology.

Conclusion

Viswanath Mohan's contributions to the field of semiconductor technology through his patents demonstrate his commitment to innovation and excellence. His work continues to influence the development of advanced processor technologies.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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