logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9842055 B1

PDFFull Text
Date of Patent:
Dec. 12, 2017

Filed:

Nov. 26, 2014

Address translation cache that supports simultaneous invalidation of common context entries

Applicant:

Via Alliance Semiconductor Co., Ltd., Shanghai, CN;

Inventors:

Colin Eddy, Austin, TX (US);

Viswanath Mohan, Austin, TX (US);

Assignee:

VIA ALLIANCE SEMICONDUCTOR CO., LTD., Shanghai, CN;

Attorneys:

E. Alan Davis

James W. Huffman

Primary Examiner:

Mano Padmanabhan

Assistant Examiner:

Jean Edouard

Int. Cl.
CPC ...
G06F 12/10 (2016.01); G06F 12/0891 (2016.01); G06F 12/1036 (2016.01); G06F 12/1045 (2016.01); G06F 15/78 (2006.01); G06F 12/1027 (2016.01); G06F 12/109 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0891 (2013.01); G06F 12/109 (2013.01); G06F 12/1027 (2013.01); G06F 12/1036 (2013.01); G06F 12/1063 (2013.01); G06F 15/7839 (2013.01);
Abstract

A processor includes a mapping module that maps architectural virtual processor identifiers to non-architectural global identifiers and maps architectural process context identifiers to non-architectural local identifiers. The processor also includes a translation-lookaside buffer (TLB) having a plurality of address translations. For each address translation of the plurality of address translations: when the address translation is a global address translation, the address translation is tagged with a representation of one of the non-architectural global identifiers to which the mapping module has mapped one of the virtual processor identifiers; and when the address translation is a local address translation, the address translation is tagged with a representation of one of the non-architectural local identifiers to which the mapping module has mapped one of the process context identifiers.

Find Patent Forward Citations

Eddy, Colin. (2017). Address translation cache that supports simultaneous invalidation of common context entries (U.S. Patent No. 9842055). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9842055

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Loading…