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For the Inventor, By the Inventor

Noida, India

Vinaya Kumar Singh

USPTO Granted Patents = 9

Average Co-Inventor Count = 3.5

ph-index = 4

Forward Citations = 50(Granted Patents)


Company Filing History:

goldMedal9 out of 2,545 
 
Cadence Design Systems, Inc.
 patents

Years Active: 2008-2014

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9 patents (USPTO):Explore Patents
1. 8671395 - Adaptive deadend avoidance in constrained simulation (2014-03-11),
2. 8104001 - Automated debugging method for over-constrained circuit verification environment (2012-01-24),
3. 8099696 - Method for providing information associated with an over-constrained event in verification of a circuit design (2012-01-17),
4. 8099695 - Automated debugging method and system for over-constrained circuit verification environment (2012-01-17),
5. 7984401 - Method for checking a status of a signal port to identify an over-constrained event (2011-07-19),
6. 7810056 - Method and system for implementing context aware synthesis of assertions (2010-10-05),
7. 7712060 - Method and system for handling assertion libraries in functional verification (2010-05-04),
8. 7428712 - Design optimization using approximate reachability analysis (2008-09-23),
9. 7386813 - Transformation of simple subset of PSL into SERE implication formulas for verification with model checking and simulation engines using semantic preserving rewrite rules (2008-06-10),

Title: Innovations by Vinaya Kumar Singh

Introduction

Vinaya Kumar Singh is a prominent inventor based in Noida, India. He has made significant contributions to the field of circuit verification and simulation. With a total of 9 patents to his name, Singh has established himself as a key figure in technological advancements.

Latest Patents

Singh's latest patents include innovative methods that enhance simulation processes. One of his notable inventions is the "Adaptive deadend avoidance in constrained simulation." This method focuses on analyzing deadends during simulations and determining constraints that may lead to these deadends. By defining lookahead constraints, the method allows for rerunning previous cycles in simulations, thereby improving efficiency.

Another significant patent is the "Automated debugging method for over-constrained circuit verification environment." This invention provides an automated system for debugging over-constrained environments. It collects useful information related to circuit evaluation, including clock cycles of over-constrained events and the identification of constraints that lead to such events. This innovation streamlines the debugging process and enhances the reliability of circuit verification.

Career Highlights

Vinaya Kumar Singh is currently employed at Cadence Design Systems, Inc., where he continues to develop cutting-edge technologies. His work has had a profound impact on the field of electronic design automation. Singh's expertise in simulation and debugging has positioned him as a leader in his domain.

Collaborations

Throughout his career, Singh has collaborated with notable professionals in the industry, including Amir Lehavot and Joezac John Zachariah. These collaborations have further enriched his work and contributed to the development of innovative solutions in circuit verification.

Conclusion

Vinaya Kumar Singh's contributions to the field of circuit verification and simulation are noteworthy. His innovative patents and career achievements reflect his dedication to advancing technology. As he continues to work at Cadence Design Systems, Singh is poised to make even more significant impacts in the future.

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