The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 2012
Filed:
Oct. 31, 2008
Amir Lehavot, San Francisco, CA (US);
Vinaya Kumar Singh, Noida, IN;
Joezac John Zachariah, Noida, IN;
Jose Barandiaran, Austin, TX (US);
Axel Siegfried Scherer, Salem, MA (US);
Amir Lehavot, San Francisco, CA (US);
Vinaya Kumar Singh, Noida, IN;
Joezac John Zachariah, Noida, IN;
Jose Barandiaran, Austin, TX (US);
Axel Siegfried Scherer, Salem, MA (US);
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which an over-constrained event occurs; identification of a minimum subset of constraints that will cause an over-constrained event to occur; signal ports having an associated signal that can not switch between different signal states; whether a triggering signal event has occurred during the evaluation; indicating whether constraints in the evaluation are realizable, etc. Novel approaches for detecting and obtaining the useful information also are described.