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Austin, TX, United States of America

Jose Barandiaran

This inventor holds 4 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2011-2012.

USPTO Granted Patents = 4

% Patents Active = 100.0

Average Co-Inventor Count = 5.0

ph-index = 3

Forward Citations = 19(Granted Patents)

Company Filing History:

Cadence Design Systems, Inc.

Years Active: 2011-2012

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4 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8104001 - Automated debugging method for over-constrained circuit verification environment (2012-01-24),

2. 8099696 - Method for providing information associated with an over-constrained event in verification of a circuit design (2012-01-17),

3. 8099695 - Automated debugging method and system for over-constrained circuit verification environment (2012-01-17),

4. 7984401 - Method for checking a status of a signal port to identify an over-constrained event (2011-07-19),

Profile summary based on public USPTO records.

Please report any incorrect information to [email protected]

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