Tsukasa Ebihara

Title: Tsukasa Ebihara: Innovator in SEU-Tolerant Circuit Design

Introduction

Tsukasa Ebihara is a notable inventor based in Kawasaki, Japan. He has made significant contributions to the field of electronics, particularly in the design of circuits that are resilient to single event upsets (SEUs). His innovative work has implications for various applications, especially in aerospace and high-reliability systems.

Latest Patents

Ebihara holds a patent for a "Single event upset-tolerant latch circuit and flip-flop circuit." This invention provides a latch circuit and a flip-flop circuit that exhibit enhanced tolerance to single event upset (SEU). The SEU-tolerant latch circuit is designed with three redundant transistors added to each of the eight transistors that make up a conventional DICE latch circuit. This configuration includes a serial position, a parallel position, and a parallel-serial position, resulting in a four-transistor circuit that duplicates a serially duplicated circuit in parallel. Additionally, both the first and second data input parts are made dually redundant.

Career Highlights

Throughout his career, Tsukasa Ebihara has worked with esteemed organizations such as the Japan Aerospace Exploration Agency and High-Reliability Engineering & Components Corporation. His experience in these institutions has allowed him to develop and refine his expertise in circuit design and reliability.

Collaborations

Ebihara has collaborated with notable colleagues, including Akifumi Maru and Satoshi Kuboyama. These partnerships have contributed to the advancement of technology in their respective fields.

Conclusion

Tsukasa Ebihara's contributions to SEU-tolerant circuit design highlight his innovative spirit and dedication to enhancing electronic reliability. His work continues to influence the industry and pave the way for future advancements in technology.