Japan Aerospace Exploration Agency

High-reliability Engineering & Components Corporation

Tsukasa Ebihara

Satoshi Kuboyama

Akiko Makihara

Akifumi Maru

Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.

Growing community of inventors

Kawasaki, Japan

Tsukasa Ebihara