The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 07, 2021
Filed:
May. 16, 2018
Japan Aerospace Exploration Agency, Tokyo, JP;
High-reliability Engineering & Components Corporation, Tsukuba, JP;
Akifumi Maru, Tokyo, JP;
Satoshi Kuboyama, Tokyo, JP;
Tsukasa Ebihara, Kawasaki, JP;
Akiko Makihara, Tsukuba, JP;
Japan Aerospace Exploration Agency, Tokyo, JP;
High-Reliability Engineering & Components Corporation, Tsukuba, JP;
Abstract
Provided are a latch circuit and a flip-flop circuit each having more excellent tolerance to single event upset (SEU). The single event upset (SEU)-tolerant latch circuit of the present invention is configured such that three transistors for redundancy are added to each of eight transistors constituting a conventional DICE latch circuit, at respective positions consisting of a serial position, a parallel position and a parallel-serial position so as to form a four-transistor circuit in which a serially duplicated circuit is duplicated in parallel, and each of a first data input part and a second data input part is also made dually redundant.