Akifumi Maru

Title: Akifumi Maru: Innovator in SEU-Tolerant Circuit Design

Introduction

Akifumi Maru is a notable inventor based in Tokyo, Japan. He has made significant contributions to the field of electronics, particularly in the design of circuits that are resilient to single event upsets (SEUs). His innovative work has implications for various applications, especially in aerospace and high-reliability systems.

Latest Patents

Maru holds a patent for a "Single event upset-tolerant latch circuit and flip-flop circuit." This invention provides a latch circuit and a flip-flop circuit that exhibit enhanced tolerance to single event upset (SEU). The SEU-tolerant latch circuit is designed with three redundant transistors added to each of the eight transistors in a conventional DICE latch circuit. This configuration creates a four-transistor circuit that duplicates a serially duplicated circuit in parallel, ensuring dual redundancy in both the first and second data input parts.

Career Highlights

Throughout his career, Akifumi Maru has worked with prestigious organizations, including the Japan Aerospace Exploration Agency and High-Reliability Engineering & Components Corporation. His experience in these institutions has allowed him to apply his innovative ideas in high-stakes environments, contributing to advancements in technology.

Collaborations

Maru has collaborated with notable colleagues such as Satoshi Kuboyama and Tsukasa Ebihara. These partnerships have fostered a creative environment that has led to the development of groundbreaking technologies.

Conclusion

Akifumi Maru's contributions to SEU-tolerant circuit design highlight his role as an influential inventor in the field of electronics. His innovative patent and collaborations with esteemed colleagues underscore the importance of resilience in modern circuit design.