Hyogo, Japan

Toshiaki Tarui

This inventor holds 1 USPTO granted patent. Top assignee: Renesas Technology Corp.. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Toshiaki Tarui. Retrieved from https://idiyas.com/inventor/toshiaki-tarui-kpcwd00n

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


Average Co-Inventor Count = 4.0

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Toshiaki Tarui: Inventor of an Analog-Signal Test Circuit.

Introduction

Toshiaki Tarui is an inventor associated with Hyogo, Japan, and Renesas Technology Corp. His patent work addresses testing the analog signal characteristics of electronic devices.

Latest Patents

Tarui is named on one patent: “Test Circuit for Evaluating Characteristic of Analog Signal of Device.” The invention combines a determination circuit, an analog-to-digital converter (ADC), and an analysis unit. The determination circuit checks whether the timing of a signal waveform’s slope section falls within specified limits. The ADC converts the signal only while its potential is between reference levels VOL and VOH, and the analysis unit evaluates the resulting digital data to assess the waveform’s slope.

This approach allows the signal’s slope to be tested across selected voltage sections without requiring a large-capacity storage circuit. It also enables the timing function test and the slope waveform test to run in parallel.

Career Highlights

Tarui’s listed patent count is 1 patent. His work reflects an engineering focus on efficient testing of analog signals and device characteristics.

Collaborations

The patent information lists Masaru Sugimoto and Hisaya Mori as Tarui’s coworkers. The available details do not specify their roles in the invention or their working relationship with him.

Conclusion

Toshiaki Tarui’s patent describes a practical circuit for evaluating analog-signal waveforms while reducing storage requirements and allowing parallel testing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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