Sunnyvale, CA, United States of America

Timour T Paltashev

This inventor holds 33 USPTO granted patents and 3 published patent applications, primarily in Graphics Processing. Top assignees: Via Technologies, Inc., Advanced Micro Devices Corporation, S3 Graphics Co., Ltd.. Active years: 2006-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Timour T Paltashev. Retrieved from https://idiyas.com/inventor/timour-t-paltashev

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 33 

% Patents Active = 100.0

Average Co-Inventor Count = 2.8

ph-index = 10

Forward Citations = 316(Granted Patents)


Location History:

  • Laveen, AZ (US) (2014 - 2015)
  • Sunnyvale, CA (US) (2017 - 2020)
  • Fremont, CA (US) (2006 - 2021)
  • Santa Clara, CA (US) (2020 - 2023)

Company Filing History:


Years Active: 2006-2025

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Areas of Expertise:
GPU Coprocessor
Graphics Pipeline
Tessellation
Data Compression
Rasterization
Video Processing
Micropolygon Rasterizers
Cache System
Instruction Width
Asynchronous Submission
Triangle Interpolation
Context Management
33 patents (USPTO):Explore Patents

Title: Innovating Graphics Processing: The Contributions of Timour T Paltashev

Introduction: Timour T Paltashev is a prolific inventor based in Sunnyvale, CA, known for his significant contributions to graphics processing technology. With an impressive portfolio of 32 patents, Timour has been at the forefront of innovation, particularly in the development of low power and low latency GPU coprocessors that enhance computing efficiency.

Latest Patents: One of Timour's latest patents focuses on low power and low latency GPU coprocessors for persistent computing. This invention outlines systems, apparatuses, and methods for implementing a graphics processing unit (GPU) coprocessor that includes a SIMD (Single Instruction, Multiple Data) unit capable of self-scheduling sub-wave procedures based on input data flow events. The coprocessor utilizes a queue system where a host processor sends messages targeting the GPU. Upon detecting a message, the coprocessor schedules a sub-task for execution. Notably, this GPU coprocessor incorporates an inter-lane crossbar and intra-lane biased indexing mechanism for a vector general purpose register (VGPR) file, which is meticulously designed to improve performance by splitting the VGPR into two distinct files. The primary file is a larger register with limited ports, while the secondary file features multiple read ports, allowing for the co-issuing of multiple instructions per clock cycle, thereby boosting efficiency and processing power.

Career Highlights: Timour has worked with notable companies in the tech industry, including Via Technologies, Inc. and Advanced Micro Devices Corporation. His experiences in these environments have played a pivotal role in shaping his innovative ideas and advancing his inventions in graphics processing technologies.

Collaborations: Throughout his career, Timour has collaborated with talented industry professionals such as Boris Prokopenko and John Wakefield Brothers. Their joint efforts have often contributed to refining and enhancing the technological advancements brought forth by Timour’s inventions.

Conclusion: Timour T Paltashev's contributions to the field of graphics processing are marked by his focus on efficiency and innovation. His work on low power and low latency GPU coprocessors underscores a commitment to pushing the boundaries of technology, making him a valuable innovator in today’s competitive landscape. As he continues to develop new solutions, the impact of his inventions will surely resonate in the future of computing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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