The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 04, 2018
Filed:
Dec. 30, 2015
Applicant:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Inventors:
Timour T. Paltashev, Sunnyvale, CA (US);
Boris Prokopenko, Sunnyvale, CA (US);
Vladimir V. Kibardin, Sunnyvale, CA (US);
Assignee:
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 17/20 (2006.01); G06T 15/00 (2011.01); G06T 1/20 (2006.01);
U.S. Cl.
CPC ...
G06T 17/20 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01);
Abstract
A method, a system, and a computer-readable storage medium directed to performing high-speed parallel tessellation of 3D surface patches are disclosed. The method includes generating a plurality of primitives in parallel. Each primitive in the plurality is generated by a sequence of functional blocks, in which each sequence acts independently of all the other sequences.
Paltashev, Timour. (2018). Method and apparatus for performing high throughput tessellation (U.S. Patent No. 10068372). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/10068372
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile