San Jose, CA, United States of America

Thomas A Kamp

This inventor holds 3 USPTO granted patents. Top assignee: Lam Research Corporation. Active years: 2006-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Thomas A Kamp. Retrieved from https://idiyas.com/inventor/thomas-a-kamp

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 33.3

Average Co-Inventor Count = 4.0

ph-index = 2

Forward Citations = 6(Granted Patents)


Company Filing History:


Years Active: 2006-2010

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3 patents (USPTO):Explore Patents

Title: Thomas A. Kamp: Semiconductor Process Inventor

Introduction

Thomas A. Kamp is an inventor based in San Jose, California, whose patent work addresses semiconductor manufacturing processes. He is associated with Lam Research Corporation and is credited with 3 patents.

Latest Patents

One of Kamp’s listed patents, “Method to Improve Profile Control and N/P Loading in Dual Doped Gate Applications,” describes a method for etching a polysilicon gate structure in a plasma etch chamber. The process defines a pattern to protect the polysilicon film, generates plasma, and etches the unprotected portion of the film. A silicon-containing gas is then introduced while the remaining polysilicon is etched. The patent also describes an etch chamber configured to introduce this gas during processing.

Career Highlights

Kamp’s patent work reflects a focus on plasma etching and process control in semiconductor fabrication. The described method uses silicon-containing gas during etching to address profile control and N/P loading in dual-doped gate applications.

Collaborations

Kamp’s listed coworkers include Alan Jeffrey Miller and Helene Del Puppo. His association with Lam Research Corporation places his work within the semiconductor equipment and manufacturing field.

Conclusion

Thomas A. Kamp’s patents document contributions to semiconductor etching, including a process designed to improve profile control and N/P loading in dual-doped gate applications.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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