Patparganj, India

Tara Vishin

This inventor holds 3 USPTO granted patents. Top assignee: Cadence Design Systems, Inc.. Active years: 2017-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Tara Vishin. Retrieved from https://idiyas.com/inventor/tara-vishin

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 2.4

ph-index = 2

Forward Citations = 14(Granted Patents)


Location History:

  • Patparganj, IN (2017 - 2018)
  • Delhi, IN (2018)

Company Filing History:


Years Active: 2017-2018

Loading Chart...
3 patents (USPTO):Explore Patents

Title: Innovations by Tara Vishin

Introduction

Tara Vishin is an accomplished inventor based in Patparganj, India. She has made significant contributions to the field of electronic design, particularly in high-speed memory drivers. With a total of 3 patents to her name, Tara is recognized for her innovative approaches to circuit design and memory device compatibility.

Latest Patents

Tara's latest patents include groundbreaking methods and devices for charge pump level translation in high-speed memory drivers. These embodiments relate to circuits, electronic design assistance (EDA) circuit layouts, systems, methods, and computer-readable media that enable logic devices operating on a core supply voltage to drive memory devices operating on different supply voltages. One embodiment features a programmable level translator device implemented using an NMOS transistor pair and a PMOS cross quad. The switching characteristics are enhanced through a charge pump connected to the gate terminals of two PMOS transistors within the PMOS cross quad. Additionally, transmission gates are employed to engage and disengage the charge pump based on a control switch. This level translator device is designed to work with various memory devices operating over a wide range of power supply voltages.

Another notable patent is the LevelShifter-less output buffer with a hybrid driver for high-speed and low-supply memory applications. This architecture for an output driver does not utilize level shifters in the high-speed data path, resulting in improved performance across PVT corners. The proposed output driver employs a hybrid pull-up driver, making it compatible with a wide range of DRAM supply voltages. This innovative approach allows for significant savings in electronic design area and dynamic power.

Career Highlights

Tara Vishin is currently employed at Cadence Design Systems, Inc., where she continues to push the boundaries of electronic design. Her work has been instrumental in developing solutions that enhance the performance and efficiency of memory devices.

Collaborations

Tara collaborates with talented professionals in her field, including Vinod Kumar and Sachin Ramesh Gugwad. Their combined expertise contributes to the innovative projects at Cadence Design Systems.

Conclusion

Tara Vishin's contributions to electronic design and her innovative patents highlight her role as a leading inventor in the industry. Her work continues to influence the development of high-speed memory technologies, showcasing her commitment to advancing the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…