The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 12, 2018
Filed:
Jun. 29, 2017
Levelshifter-less output buffer with hybrid driver for high speed and low supply memory applications
Applicant:
Cadence Design Systems, Inc., San Jose, CA (US);
Inventors:
Vinod Kumar, Uttar Pradesh, IN;
Tara Vishin, Delhi, IN;
Assignee:
Cadence Design Systems, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 14/00 (2006.01); G11C 5/14 (2006.01); G11C 11/40 (2006.01); H03K 19/173 (2006.01); H03K 19/00 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
G11C 7/1057 (2013.01); G11C 5/147 (2013.01); G11C 11/40 (2013.01); G11C 14/0009 (2013.01); H03K 19/0005 (2013.01); H03K 19/018521 (2013.01); H03K 19/1733 (2013.01);
Abstract
Disclosed is an architecture for an output driver that does not employ level shifters in the high speed data path. Since the proposed architecture is free from level shifters in the high speed data path, it provides better performance across PVT corners. The disclosed output driver usages a hybrid pullup driver which makes it compatible for the wide range of DRAM supply range. This approach allows for significant savings for electronic design area and dynamic power.