Niigata, Japan

Takeshi Onozuka

This inventor holds 1 USPTO granted patent. Top assignee: Globalwafers Japan Co., Ltd.. Active years: 2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takeshi Onozuka. Retrieved from https://idiyas.com/inventor/takeshi-onozuka

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile


% Patents Active = 100.0

Average Co-Inventor Count = 3.0

ph-index = 1


Company Filing History:


Years Active: 2022

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1 patent (USPTO):Explore Patents

Title: The Innovations of Takeshi Onozuka

Introduction

Takeshi Onozuka is a notable inventor based in Niigata, Japan. He has made significant contributions to the field of semiconductor technology, particularly in evaluating metal contamination in silicon wafers. His work is essential for improving the quality and performance of semiconductor devices.

Latest Patents

Takeshi Onozuka holds a patent for an "Evaluation method of metal contamination." This innovative method involves measuring the amount of metal contaminants on a silicon wafer within a rapid thermal processing apparatus. The process includes obtaining a silicon single crystal grown by the Czochralski method, slicing silicon wafers, heat-treating them, and measuring the lifetime of the silicon wafer after contaminants are transferred.

Career Highlights

Onozuka is currently employed at Globalwafers Japan Co., Ltd., where he continues to advance his research and development efforts. His expertise in semiconductor technology has positioned him as a valuable asset in the industry.

Collaborations

Throughout his career, Takeshi has collaborated with notable colleagues, including Nobue Araki and Tomoyuki Ishihara. These partnerships have fostered innovation and contributed to the success of their projects.

Conclusion

Takeshi Onozuka's work in evaluating metal contamination in silicon wafers showcases his dedication to advancing semiconductor technology. His contributions are vital for the ongoing development of high-quality semiconductor devices.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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