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For the Inventor, By the Inventor

Yokohama, Japan

Takayuki Kamei

This inventor holds 5 USPTO granted patents. Top assignee: Kabushiki Kaisha Toshiba. Active years: 2003-2008.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Takayuki Kamei. Retrieved from https://idiyas.com/inventor/takayuki-kamei

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5

% Patents Active = 20.0

Average Co-Inventor Count = 2.7

ph-index = 2

Forward Citations = 32(Granted Patents)


Location History:

  • Sagamihara, JP (2003)
  • Ssagamihara, JP (2006)
  • Yokohama, JP (2004 - 2008)

Company Filing History:

goldMedal5 out of 53,262 
 
Kabushiki Kaisha Toshiba
 patents

Years Active: 2003-2008

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5 patents (USPTO):Explore Patents
1. 7356798 - Semiconductor integrated circuit routing method and recording medium which stores routing software (2008-04-08),
2. 7290225 - Method for compressing semiconductor integrated circuit, using design region divided into plural blocks (2007-10-30),
3. 7042448 - Image processing unit, image processing system using the same, and image processing method (2006-05-09),
4. 6741100 - Semiconductor integrated circuit capable of high-speed circuit operation (2004-05-25),
5. 6587110 - Image processing unit, image processing system using the same, and image processing method (2003-07-01),

Title: **Innovative Contributions of Takayuki Kamei in Semiconductor Technology**

Introduction

Takayuki Kamei is a prominent inventor based in Yokohama, Japan, known for his significant contributions to the field of semiconductor technology. With a total of five patents to his name, Kamei has demonstrated a strong commitment to innovation, particularly in the development of routing methods and design compression for integrated circuits.

Latest Patents

Among his latest patents, Kamei has developed a semiconductor integrated circuit routing method and a recording medium that stores routing software. This method involves receiving wiring enable/disable information for respective terminals, determining the connection capability of wiring lines, and executing connections based on specific enable/disable criteria. Moreover, Kamei’s method for compressing semiconductor integrated circuits includes dividing a design region into several blocks and optimizing the density of semiconductor devices within these blocks to enhance performance while ensuring effective connectivity.

Career Highlights

Kamei is currently employed at Kabushiki Kaisha Toshiba, a leading company in the electronics and semiconductor industry. His work in the company not only showcases his technical expertise but also highlights his role in advancing cutting-edge technologies in semiconductors.

Collaborations

Throughout his career, Kamei has collaborated with talented colleagues such as Atsushi Kunimatsu and Kiyoji Ueno. These collaborations have further enriched his work, enabling him to bring innovative solutions to complex engineering challenges within the semiconductor space.

Conclusion

In summary, Takayuki Kamei stands out as an influential inventor with a strong portfolio of patents in semiconductor technology. His latest innovations reflect his dedication to advancing the field, making substantial contributions that can shape future developments in integrated circuits and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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