The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7290225 B1

PDF
Full Text
Expired
Date of Patent:
Oct. 30, 2007

Filed:

Oct. 06, 2003
Applicants:

Naoyuki Tamura, Kawasaki, JP;

Takayuki Kamei, Yokohama, JP;

Inventors:

Naoyuki Tamura, Kawasaki, JP;

Takayuki Kamei, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G07F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for compressing a semiconductor integrated circuit, comprising dividing a design region, in which a semiconductor integrated circuit is to be designed, into a plurality of blocks, assigning semiconductor devices to each of the blocks, determining a device density of each block, compressing any block, and connecting the blocks by wiring. In the compressing of the block, the block that is determined to have a low device density is compressed.


Find Patent Forward Citations

Tamura, Naoyuki. (2007). Method for compressing semiconductor integrated circuit, using design region divided into plural blocks (U.S. Patent No. 7290225). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7290225

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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