The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 25, 2004

Filed:

Jun. 21, 2002
Applicant:
Inventors:

Yasuhito Itaka, Yokohama, JP;

Takayuki Kamei, Yokohama, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 1/900 ;
U.S. Cl.
CPC ...
H03K 1/900 ;
Abstract

In a standard cell, rise time when an output transitions from a low-level voltage to a high-level voltage and fall time when an output transitions from the high-level voltage to the low-level voltage differ from each other. A flip-flop outputs a first input signal, which is input in a cycle immediately before a clock in synchronization with one of rise and fall of the clock, to the standard cell and then fixes an output the signal at one of a high-level voltage and a low-level voltage. Before a second input signal, which is output from the flip-flop after the first input signal, reaches the standard cell, an output of the standard cell is set at one of a high-level voltage and a low-level voltage, which corresponds to a signal whose transition speed is slow, by one of the high-level voltage and the low-level voltage that is output from the flip-flop.


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