Location History:
- Watertown, MA (US) (2006)
- Newton, MA (US) (2013)
Company Filing History:
Years Active: 2006-2013
Title: Surrendra A Dudani: Innovator in Circuit Verification Technologies
Introduction
Surrendra A Dudani is a notable inventor based in Newton, MA (US). He has made significant contributions to the field of circuit verification, holding a total of 3 patents. His work focuses on enhancing the reliability and efficiency of circuit designs through innovative methodologies.
Latest Patents
One of Dudani's latest patents is titled "Constrained random simulation coverage closure guided by a cover property." This invention provides a system that verifies circuit designs by biasing input stimuli to satisfy temporal coverage properties. The system utilizes a finite state automaton (FSA) instance to observe inputs and outputs, applying soft constraints to guide the simulation effectively.
Another significant patent is "Vector evaluation of assertions." This patent describes systems and techniques for evaluating assertions during circuit verification. It identifies semantically equivalent assertions and evaluates them in parallel using a set of vectors, enhancing the efficiency of the verification process.
Career Highlights
Surrendra A Dudani is currently employed at Synopsys, Inc., a leading company in electronic design automation. His work at Synopsys has allowed him to develop and refine technologies that are crucial for circuit design verification.
Collaborations
Dudani has collaborated with notable professionals in his field, including Eduard Rudolf Cerny and Debashis Roy Chowdhury. These collaborations have contributed to the advancement of circuit verification technologies.
Conclusion
Surrendra A Dudani's innovative work in circuit verification has made a significant impact on the industry. His patents reflect a commitment to improving the reliability of circuit designs, showcasing his expertise and dedication to technological advancement.