Synopsys, Inc.

Surrendra A Dudani

Eduard Rudolf Cerny

William R Dufresne

Debashis Roy Chowdhury

Pallab Kumar Dasgupta

Samik Sengupta

Ghassan Khoory

One embodiment of the present invention provides a system which verifies a circuit design by biasing input stimuli for the circuit design to satisfy one or more temporal coverage properties to be verified for the circuit design. This system performs a simulation in which random input stimuli are applied to the circuit design. The system performs the simulation by using a finite state automaton (FSA) instance for a temporal coverage property to observe inputs and outputs of the circuit, and by using soft constraints associated with the FSA instance to bias the input stimuli for the circuit design so that the simulation is likely to progress through a sequence of states which satisfy the temporal coverage property.

Constrained random simulation coverage closure guided by a cover property

Systems and techniques for evaluating assertions during circuit verification are described. During operation, m semantically equivalent assertions can be identified, wherein each of the m semantically equivalent assertions is evaluated using n logical expressions. Next, a set of vectors based on the m semantically equivalent assertions can be determined, wherein each vector element corresponds to a logical expression that is used for evaluating one of the m semantically equivalent assertions. The m semantically equivalent assertions can then be evaluated, in parallel, using the set of vectors.

Vector evaluation of assertions

A technique for observability based coverage of a design under test (DUT) is presented. A conventional simulation signal is augmented to include a 'tag value.' In the course of a simulation, assignment statements (for which observability-based coverage is desired) 'inject' tag values on their output signals. A tag value contains an identifier uniquely identifying the assignment statement that produced it. A tag value also contains a &#x201c;tag history.&#x201d; The tag history contains copies of the tag values for assignment statements earlier in the flow of control or in the flow of data. If a tag propagated through the DUT appears at an observable output, the circuit designer knows that the assignment statements it identifies have satisfied observability based coverage.

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Newton, MA, United States of America

Surrendra A Dudani