San Jose, CA, United States of America

Suresh Subramaniam

This inventor holds 5 USPTO granted patents. Top assignee: Apex Semiconductor. Active years: 2021-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suresh Subramaniam. Retrieved from https://idiyas.com/inventor/suresh-subramaniam

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 3.7

ph-index = 3

Forward Citations = 39(Granted Patents)


Company Filing History:


Years Active: 2021-2022

Loading Chart...
5 patents (USPTO):Explore Patents

Title: Innovations by Suresh Subramaniam in Integrated Circuit Design

Introduction

Suresh Subramaniam is a notable inventor based in San Jose, CA, who has made significant contributions to the field of integrated circuit design. With a total of 5 patents to his name, he has developed innovative techniques that enhance the performance and reliability of electronic devices.

Latest Patents

One of his latest patents is titled "Multi-PVT frequency prediction (multi-PVT FP) for statically timed designs through statistical regression." This invention improves integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through statistical analysis. A design management component (DMC) can determine a trained model representing timing path properties and operating conditions of agnostic timing paths based on an analysis of vectorized data that represents timing path information associated with the agnostic timing paths. The DMC can perform statistical regression on the vectorized data to facilitate training the trained model. Additionally, a static timing analysis (STA) component can perform STA on design information associated with the integrated circuitry design and determine an operating condition of a timing path of the integrated circuitry design based on the STA. The DMC can predict or determine at least one other operating condition associated with the integrated circuitry design based on the operating condition and the trained model.

Another significant patent is focused on "Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction." This invention also improves integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. The DMC can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, with the parameters determined based on random seed values. It can simulate responses of the sample timing paths and generate vectorized data based on the simulated responses. The DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. The STA component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. The DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.

Career Highlights

Suresh Subramaniam currently works at Apex Semiconductor, where he continues to innovate and contribute to advancements in

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…