The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 24, 2021

Filed:

Apr. 27, 2020
Applicant:

Apex Semiconductor;

Inventors:

Suresh Subramaniam, San Jose, CA (US);

Alfred Yeung, San Jose, CA (US);

Assignee:

Apex Semiconductor, San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4027 (2013.01); G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01);
Abstract

A flexible standards-based bridge or switch chiplet facilitates heterogeneous integration of chiplets that support different physical layer (PHY) interfaces and communication protocols. The bridge chiplet is configured with multiple PHY interfaces and associated adapter logic and translation logic for translation between different PHY interfaces and protocols. The bridge chiplet can be programmed to serve as a die-to-die interconnect bridge that routes data between multiple chiplets supporting different PHYs and interconnect protocols. Some embodiments of the bridge chiplet can serve solely as a PHY bridge, while others may serve as a bridge for both PHYs and protocols.


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