Clifton Park, NY, United States of America

Suresh Kumar Regonda

This inventor holds 2 USPTO granted patents and 1 published patent application. Top assignees: Globalfoundries Inc., Globalfoundries U.S. Inc.. Active years: 2017-2021.

USPTO Granted Patents = 2 

% Patents Active = 50.0

Average Co-Inventor Count = 5.5

ph-index = 1

Forward Citations = 2(Granted Patents)


Company Filing History:


Years Active: 2017-2021

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2 patents (USPTO):Explore Patents

Title: Innovations by Suresh Kumar Regonda

Introduction

Suresh Kumar Regonda is an accomplished inventor based in Clifton Park, NY (US). He has made significant contributions to the field of integrated circuit technology, particularly in memory devices and transistor fabrication. With a total of two patents to his name, Regonda's work showcases his expertise and innovative approach to solving complex engineering challenges.

Latest Patents

Regonda's latest patents include methods for forming a conductive contact structure to a top electrode of an embedded memory device on an integrated circuit product. One illustrative method involves selectively forming a sacrificial material on the upper surface of a top electrode of a memory cell. This process includes forming at least one layer of insulating material around the sacrificial material and subsequently removing the sacrificial material to create an opening that exposes the upper surface of the top electrode. Additionally, the method incorporates forming an internal sidewall spacer within the opening and establishing a conductive contact structure that is conductively coupled to the upper surface of the top electrode.

Another notable patent focuses on stress memorization techniques for transistor devices. This method involves fabricating an NMOS transistor device with a substrate and a gate structure. The process includes performing a nitrogen ion implantation to create a stress region in the substrate, which is separated by the channel region. The method also entails forming a capping material layer above the NMOS transistor device and conducting a stress forming anneal process to create stacking faults in

Profile summary based on public USPTO records.
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