Milpitas, CA, United States of America

Surendra Rathaur

This inventor holds 1 USPTO granted patent. Top assignee: Intel Corporation. Active years: 2006.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Surendra Rathaur. Retrieved from https://idiyas.com/inventor/surendra-rathaur

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 7.0

ph-index = 1

Forward Citations = 13(Granted Patents)


Company Filing History:


Years Active: 2006

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1 patent (USPTO):Explore Patents

Title: Surendra Rathaur: Innovator in Hardware and Software Co-Simulation

Introduction

Surendra Rathaur is a notable inventor based in Milpitas, CA (US). He has made significant contributions to the field of hardware and software co-simulation, particularly in the development of Application-Specific Integrated Circuits (ASICs). His innovative approach has streamlined the development process, allowing for concurrent hardware and software development.

Latest Patents

Surendra Rathaur holds a patent for a "Method and apparatus for hardware and software co-simulation." This invention provides a method and apparatus that enables the concurrent development of hardware and software, facilitating co-simulation via a network. This approach allows software development and testing to commence alongside hardware design, effectively reducing the overall system development cycle for ASICs. He has 1 patent to his name.

Career Highlights

Surendra Rathaur is currently employed at Intel Corporation, a leading technology company known for its innovations in semiconductor manufacturing and computing technologies. His work at Intel has positioned him at the forefront of advancements in hardware and software integration.

Collaborations

Some of his notable coworkers include Miguel A Guerrero and Simon Luigi Sabato. Their collaboration has likely contributed to the innovative environment at Intel, fostering advancements in technology.

Conclusion

Surendra Rathaur's contributions to hardware and software co-simulation represent a significant advancement in the field of ASIC development. His innovative methods have the potential to greatly enhance the efficiency of technology development processes.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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