Cheongju, South Korea

Sung Hoon Lee

This inventor holds 2 USPTO granted patents. Top assignees: Db Hitek Co., Ltd., Db Hitek Co., Ltd.. Active years: 2025-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Sung Hoon Lee. Retrieved from https://idiyas.com/inventor/sung-hoon-lee-g8yzb7ph

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

% Patents Active = 100.0

Average Co-Inventor Count = 1.6

ph-index = 1

Forward Citations = 1(Granted Patents)


Company Filing History:


Years Active: 2025-2026

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2 patents (USPTO):Explore Patents

Title: Sung Hoon Lee: Semiconductor Device Inventor

Introduction

Sung Hoon Lee is an inventor based in Cheongju, South Korea. His work focuses on semiconductor device structures and manufacturing processes. He holds 2 patents.

Latest Patents

Lee’s patent, “High Voltage Semiconductor Device Including Isolation Region,” describes an isolation region containing multiple vertically arranged voids. The design aims to reduce cracking and prevent materials such as tungsten from entering cracks during later manufacturing steps, which could otherwise impair breakdown-voltage characteristics.

His patent, “Semiconductor Device and Method for Manufacturing the Same,” concerns device-isolation structures with pre-deep-trench-isolation or deep-trench-isolation features. The structures include a cut, corner, or truncated region in plan view, with the goal of reducing defects during isolation formation and subsequent chemical mechanical polishing.

Career Highlights

Lee is associated with DB HiTek Co., Ltd., where his work relates to semiconductor devices and their fabrication.

Collaborations

His listed coworkers include Sang Il Hwang and Young Joon Choi. These associations place his patent work within a broader semiconductor engineering environment.

Conclusion

Sung Hoon Lee’s patents address practical challenges in semiconductor isolation, including crack prevention and defect reduction during manufacturing.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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