Munich, Germany

Suhas Shivapakash

This inventor holds 1 USPTO granted patent and 1 published patent application. Top assignee: Micron Technology Incorporated. Active years: 2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Suhas Shivapakash. Retrieved from https://idiyas.com/inventor/suhas-shivapakash

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 1 

Average Co-Inventor Count = 1.0

ph-index = 1


Company Filing History:


Years Active: 2026

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1 patent (USPTO):Explore Patents

Title: Suhas Shivapakash and His Patent for Clock Doubling.

Introduction

Suhas Shivapakash is an inventor based in Munich, Germany, associated with Micron Technology Incorporated. His patent work includes a technique for generating a higher-frequency clock signal from two clock signals with the same frequency but different phases.

Latest Patents

The available information lists one patent for Shivapakash: “Systems and Techniques for Clock Doubling.” The invention describes a clock adjustment circuit that uses two differently phased input clocks to generate a higher-frequency output. A duty cycle monitor tracks changes in the relative phases of the input clocks and supports corrections to help maintain a consistent output duty cycle. The design can also shorten the clock tree traversed by the higher-frequency signal, potentially reducing bias temperature instability and other forms of signal degradation. Shivapakash is associated with 1 patent.

Career Highlights

Shivapakash’s listed patent reflects work on clock generation and signal integrity, areas relevant to electronic systems. The available information identifies Micron Technology Incorporated as his company.

Collaborations

The listed coworkers associated with Shivapakash are Fabien Funfrock and Elena Cabrera Bernal.

Conclusion

Suhas Shivapakash’s clock-doubling patent describes a way to generate a higher-frequency clock while monitoring duty-cycle consistency and limiting signal degradation.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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